Aldec China HES-DVM PLD设计与仿真

One Platform – Multiple Solutions

HES-DVM provides verification teams with multiple use modes including simulation acceleration, transaction level co-emulation and in-circuit emulation for chip and system level verification of SoC and ASIC designs. These use models enable many applications like for example hardware and software co-verification utilizing TLM wrappers and high-speed AXI or AHB bus transactors to connect design residing in hardware with Virtual Platform. Such a hybrid of Emulation and Virtual Platform along with the latest embedded processors, standard peripherals, and even OS platforms makes complete SoC environment software developers can utilize.

Combined powerful debugging tools allow for 100% visibility into modules running in FPGA that makes the HES-DVM emulation platform as easy to use as RTL simulator.

Scalability and Reuse

Scalability is the main idea standing behind the HES-DVM project and something that makes our solution unique. The FPGA technology is evolving so fast that it is wise to be always on the cutting edge. Instead of limiting themselves to a fixed dedicated hardware emulation platform Aldec decided to develop an open architecture that can be quickly migrated to next generation FPGA technology and also used with custom in-house made prototyping boards. Scalability and reuse is reflected in the following fields:

• Scalable across FPGA technology, quick adoption of newest FPGA
• Supports scalable hardware platforms with backplane or extension slots
• Scalable for increasing design sizes with incremental and parallel synthesis and implementation
• Supports scalable simulation acceleration and emulation clusters
• Reuse the same hardware across different teams: simulation, emulation, prototyping

Top Features:

Supported Boards

• Off the shelf FPGA boards HES-7 by Aldec
• In-house made custom boards (with Xilinx FPGA: Virtex-5, Virtex-6, Virtex-7)

Verification Interfaces

• Simulation acceleration (various simulators: Active-HDL, Riviera-PRO, third party simulators)
• SystemVerilog DPI-C for transaction level and UVM simulation acceleration
• PLI/VHPI for bit-level acceleration
• SCE-MI and TLM for transaction level co-emulation
• Easy integration with C/C++, SystemC, Verilog, SystemVerilog, and VHDL
• Supported on Linux and MS Windows

Automated Design Setup

• Complete design setup toolset – DVM
• Design compilation front-end supporting latest standards of SystemVerilog and VHDL
• Behavioral compiler for transactors supporting SV DPI-C and Implicit State Machines (ISM)
• Incremental design synthesis with 3rd party synthesis tools
• Self-constrained and automated implementation with FPGA vendor tools (Xilinx Vivado, ISE)
• Automatic and guided partitioning
• Automatic gated clock conversion with unlimited number of clock domains
• Memory flow to map design memories to board or FPGA resources
• Debugging aware design processing with automatic code instrumentation
• Parallel computing with LSF and SGE and design setup scalability
• TCL scripting and GUI available

Debugging Capabilities

• HVD technology for 100% visibility with reduced number of captured probes
• Configurable triggering
• Hardware breakpoints
• Clocks control (Stop, Run, Step)
• Saving debug data in waveform files: ASDB for Riviera-PRO and FSDB for Verdi
• Memory back-door access for read & write
• HW Debugger tool with GUI to manage debug process also remotely via LAN.
• C/C++ HES Debug API