Cadence Design Systems Conformal PLD设计与仿真

Conformal Equivalence Checker
Cadence Conformal Equivalence Checker (EC) makes it possible to verify and debug multi-million–gate designs without using test vectors. It offers the industry’s only complete equivalence checking solution for verifying SoC designs—from RTL to final LVS netlist (SPICE)—as well as FPGA designs. Cadence Conformal EC enables designers to verify the widest variety of circuits, including complex arithmetic logic, datapaths, memories, and custom logic. Already proven in thousands of tapeouts, Conformal EC is the industry’s most widely supported independent equivalence checking product. It is production-proven on more physical design closure products, advanced synthesis software, ASIC libraries, and IP cores than any other formal verification technology.

Conformal Constraint Designer
Cadence Conformal Constraint Designer provides a complete and efficient path to develop and manage constraints and clock-domain crossings (CDCs), ensuring they are functionally correct from RTL to layout. By pinpointing real design issues quickly and accurately, delivering higher quality timing constraints, and finding issues with clock-domain synchronizers, the solution helps you reduce overall design cycle times and enhance quality of silicon in complex SoC designs. With Conformal Constraint Designer, you can reduce the risk of respins through formal validation of constraints. Since the solution quickly validates failing timing paths as functionally false, it speeds convergence for timing closure. It also creates initial constraints effortlessly with the SDC advisor.

Conformal ECO Designer
Cadence Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout, and offers early ECO prototyping capabilities for driving critical Yes/No project decisions. ECOs have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. ECOs can be a time of high stress, long work hours, and uncertainty. Even if the logic change is implemented in the netlist, there might not be enough spare gates on the mask to implement the change.

Features

• Enables front-end designers to quickly implement ECOs allowing earlier netlist handoff for implementation
• Improves designer productivity and offers flexibility to do ECO with metal-only layers, thus reducing manufacturing costs and driving faster design convergence toward tapeout
• Reduces verification time significantly by using abstraction techniques to verify multi-million–gate designs much faster than traditional gate-level simulation
• Decreases the risk of missing critical bugs through independent verification technology

Conformal Low Power
Cadence Conformal Low Power enables the creation and validation of power intent in the context of a design. Conformal technology combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs.
Optimizing designs for leakage and dynamic power helps designers reduce energy consumption and packaging costs. These advanced low-power design methods can also complicate the verification task, introducing risk during synthesis and physical implementation.

Full-chip, gate-level simulation is not a practical or scalable methodology for verifying today’s large, complex designs. Conformal low power enables designers to create power intent, then verify and debug multi-million-gate designs without simulating test vectors. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity, and ease of use.